Advanced Computer Organization & Architecture
1st Edition
9390727499
·
9789390727490
© 2021 | Published: June 25, 2021
OVERVIEWThis textbook captures the latest developments in the field of computer architecture. It is targeted towards senior undergraduate students, graduate students, and industry professionals. It starts from simple in-order processors and proceeds …
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Chapter 1 Introduction 1.1–1.9
PART I Processor Design
Chapter 2 Out-of-order Pipelines 2.3–2.36
Chapter 3 The Fetch and Decode Stages 3.1–3.31
Chapter 4 The Issue, Execute and Commit Stages 4.1–4.54
Chapter 5 Alternative Approaches to Issue and Commit (Available Online) 5.1–5.61
Chapter 6 Graphics Processors 6.1–6.36
PART II The Memory System
Chapter 7 Caches 7.3–7.80
Chapter 8 On-Chip Network 8.1–8.75
Chapter 9 Multicore Systems: Coherence, Consistency and Transactional Memory 9.1–9.118
Chapter 10 Main Memory 10.1–10.68
PART III Advanced Topics
Chapter 11 Power and Temperature (Available Online) 11.3-11.31
Chapter 12 Reliability (Available Online) 12.1–12.33
Chapter 13 Secure Processor Architectures 13.1–13.33
Chapter 14 Architectures for Machine Learning 14.1–14.34
Appendix A SimpleRisc ISA A.1–A.2
Appendix B Tejas Architectural Simulator B.1–B.5
Appendix C Intel Processors C.1–C.5
Appendix D AMD Processors D.1–D.4
Appendix E Qualcomm Processors E.1–E.3
Bibliography (Available Online) Bib.1–Bib.19
List of Trademarks T.1
Index I.1–I.11
PART I Processor Design
Chapter 2 Out-of-order Pipelines 2.3–2.36
Chapter 3 The Fetch and Decode Stages 3.1–3.31
Chapter 4 The Issue, Execute and Commit Stages 4.1–4.54
Chapter 5 Alternative Approaches to Issue and Commit (Available Online) 5.1–5.61
Chapter 6 Graphics Processors 6.1–6.36
PART II The Memory System
Chapter 7 Caches 7.3–7.80
Chapter 8 On-Chip Network 8.1–8.75
Chapter 9 Multicore Systems: Coherence, Consistency and Transactional Memory 9.1–9.118
Chapter 10 Main Memory 10.1–10.68
PART III Advanced Topics
Chapter 11 Power and Temperature (Available Online) 11.3-11.31
Chapter 12 Reliability (Available Online) 12.1–12.33
Chapter 13 Secure Processor Architectures 13.1–13.33
Chapter 14 Architectures for Machine Learning 14.1–14.34
Appendix A SimpleRisc ISA A.1–A.2
Appendix B Tejas Architectural Simulator B.1–B.5
Appendix C Intel Processors C.1–C.5
Appendix D AMD Processors D.1–D.4
Appendix E Qualcomm Processors E.1–E.3
Bibliography (Available Online) Bib.1–Bib.19
List of Trademarks T.1
Index I.1–I.11
OVERVIEW
This textbook captures the latest developments in the field of computer architecture. It is targeted towards senior undergraduate students, graduate students, and industry professionals. It starts from simple in-order processors and proceeds to cover the most elaborate techniques in out-of-order (OOO) processor design that comprise the state of the art. The book also thoroughly covers GPUs and multicore technologies including the design of modern memory systems. Nonvolatile memory technologies and the DDR-4 protocol are discussed in detail. The last part of the book covers latest advances in power/temperature modelling and management, reliability, process variation, hardware security, and the design of AI/ML accelerators
KEY FEATURES
• In-depth coverage of modern OOO pipelines and GPUs.
• Detailed description of the theoretical fundamentals underlying caches, NoCs, and memory models.
• Latest developments in the field of nonvolatile memories, reliability, and temperature modelling.
• Radically novel approach for introducing the concepts used to design AI/ML accelerators.
• Pedagogy
o Exercises – 193
o Illustrations – 416
This textbook captures the latest developments in the field of computer architecture. It is targeted towards senior undergraduate students, graduate students, and industry professionals. It starts from simple in-order processors and proceeds to cover the most elaborate techniques in out-of-order (OOO) processor design that comprise the state of the art. The book also thoroughly covers GPUs and multicore technologies including the design of modern memory systems. Nonvolatile memory technologies and the DDR-4 protocol are discussed in detail. The last part of the book covers latest advances in power/temperature modelling and management, reliability, process variation, hardware security, and the design of AI/ML accelerators
KEY FEATURES
• In-depth coverage of modern OOO pipelines and GPUs.
• Detailed description of the theoretical fundamentals underlying caches, NoCs, and memory models.
• Latest developments in the field of nonvolatile memories, reliability, and temperature modelling.
• Radically novel approach for introducing the concepts used to design AI/ML accelerators.
• Pedagogy
o Exercises – 193
o Illustrations – 416